Modern radar systems are extremely complex, and are subject to numerous types of faults which, if allowed to persist, may adversely affect the radar mission or result in damage to the radar system itself. In some cases, such as in military applications, the mission of the radar may be of extreme importance, and failure may have drastic results.
For this reason, radar systems may include inspection locations at which analog values of electrical, thermal or other parameters may be monitored to verify that they are within predetermined values deemed to be satisfactory, and so that corrective action can be taken should the values move in a direction which is deemed to be undesirable. FIG. 1 is a simplified block diagram of a Radar Transmitter Signal Processor Group Equipment portion 12 of a prior art radar system 10 with hardware and software for monitoring various analog electrical values of the radar transmitter group equipment 12. In FIG. 1, radio-frequency (RF) signals from an exciter (not illustrated) are applied by way of a path 16 to a monitor or modulator illustrated as a block 14. The RF is modulated in block 14 to produce modulated RF signal (MRFS), which is applied to a driver/predriver illustrated as a block 18. The driver/predriver amplify the modulated RF signal to produce driven RF signal (DRFS), which is applied over a path 19 to a final power amplifier (FPA) 20. The final power amplifier 20 amplifies the driven RF signal to produce power RF signal (PRFS) for application to an antenna group (not illustrated). The final power amplifier 20 receives high voltage from a high voltage power supply (HVPS) 22. The high voltage power supply may also provide high voltage to the driver/predriver 18, as suggested by dash-line conductor 17. It should be noted that the various elements of the radar transmitter signal processor group equipment portion 12, are housed in “cabinets.” This “cabinet” terminology should not be taken too literally, as each of the modulator 14, driver/predriver 18, FPA 20, and HVPS 22 may occupy several actual or physical equipment cabinets, well known in the art, which are interconnected by appropriate cabling or waveguides.
In the arrangement of FIG. 1, each of the modulator 14, driver/predriver 18, FPA 20, and HVPS 22 elements of the radar transmitter signal processor group equipment portion 12 handles electrical, thermal or other parameters which are in their actual analog form, rather than being in symbolic form such as digital equivalents. Thus, the various elements such as the modulator 14, the driver/predriver 18, the FPA 20, and the HVPS 22, require monitoring of the analog values.
In FIG. 1, a set 24 of control fault logic assemblies (CFLAs) includes a plurality of individual control fault logic assemblies. One control fault logic assembly is associated with each of the modulator 14, driver/predriver 18, final power amplifier (FPA) 20, and high voltage power supply (HVPS) 22. More particularly, a control fault logic assembly 24a is associated with the FPA 20, a control fault logic assembly 24b is associated with HVPS 22, a control fault logic assembly 24c is associated with driver/predriver 18, and a control fault logic assembly 24d is associated with the modulator 14. Each of these control fault logic assemblies 24a, 24b, 24c, and 24d receives specific addresses and commands in digital form over a bus 26 from an operational resources test system (ORTS) processor 28, and translates the addresses and commands into the analog world, by making hardware connections to the specific analog inspection location identified by the locations and commands, and by sampling the analog values and converting the sampled analog values into digital equivalents that may be sent, as by way of path 26, to monitoring equipment such as ORTS processor 28.
In the prior art arrangement of FIG. 1, a general-purpose computer 30 contains the ORTS processor 28 and a display monitor. The ORTS processor is preprogrammed with code which is responsive to sampling and execution commands from the general-purpose computer. That is, the software code with which ORTS processor 28 is loaded is written according to specific inspection requirements set by hardware engineers and entered by software engineers (represented by block 35 on FIG. 1), compiled into binary format, and linked and loaded into a build suitable for running on the computer processor 30. Once this build is created, it is static. No changes are possible without restarting the examine requirements, writing corresponding code, compiling the code, link and load code procedure, as set forth in block 35 of FIG. 1. These inspection requirements may include the analog characteristic (voltage, current, frequency, phase, temperature, and the like) to be tested, the bus location, the return bit value on the bus, which is the actual value of each and every bit at the queried address that indicates the state of the hardware, the expected bit value, and the like. If the hardware changes or bugs are found, new code must be developed to accommodate the changes. At the time that the new code is to be developed, the person developing the code may have forgotten details of the code philosophy, with the result that development of the new code may be very time-consuming as old records are reviewed. In addition, it may be expected that human error may introduce problems into the resulting code. Most importantly, when software changes and requirements are not updated to match, information may be lost.
Improved methods for inspection of hardware locations is or are desired.